This invention is in the field of voltage converters. Embodiments are more specifically directed to switched mode DC-DC voltage converter circuits.
Many electronic circuits and systems require the application of a negative DC voltage to one or more circuit nodes. For example, a negative bias may be required by certain component types, as a necessary power supply voltage to particular output devices such as displays, or to increase the performance and dynamic range of analog circuits. However, because most modern electronic devices rely on only a single, positive polarity, external DC power supply voltage, circuitry must be provided within these systems to generate a negative DC voltage from the positive external power supply voltage. Several architectures, or topologies, for DC-DC voltage converters that produce negative voltages are well-known in the art.
FIG. 1a illustrates one conventional voltage converter topology, in the form of the well-known inverting buck-boost converter. This circuit generates a negative polarity output voltage VOUT from a positive polarity input voltage VIN. Input voltage VIN is provided at the drain of n-channel metal-oxide-semiconductor (MOS) transistor T1, which has its source connected to the drain of n-channel MOS transistor T2 and to one end of inductor L, the other end of which is at ground. The output voltage VOUT appears across output capacitor COUT, at the source of transistor T2. Clock generator 2 generates complementary (typically non-overlapping) clock phases ΦA and ΦB over a periodic sequence of clock cycles. These clock phases ΦA and ΦB are applied to the gates of transistors T1 and T2, respectively. In operation during phase ΦA, transistor T1 is on, conducting current IL from input voltage VIN through inductor L, which develops a voltage VL=VA across inductor L. The inductor voltage VL corresponds to input voltage VIN minus the drain-to-source voltage drop across transistor T1. Transistor T2 is on during phase ΦB, and conducts a current IB equal to inductor current IL, pulling output voltage VOUT negative. Output capacitor COUT serves as a low-pass filter to stabilize output voltage VOUT at a voltage corresponding to the duty cycle D of phase ΦA:
      V    OUT    =      -                  V        IN            ⁡              (                  D                      1            -            D                          )            According to the inverting buck-boost converter of FIG. 1a, inductor L serves as the energy storage element, in that its inductor current IL operates to transfer energy from the input side of the circuit (transistor T1) to the output side (current IB, which is the sum of load current ILOAD and discharge current from capacitor COUT).
While the inverting buck-boost topology presents an output voltage VOUT of a magnitude that can be either greater or smaller than that of input voltage VIN, it presents certain drawbacks and limitations that are undesirable in many applications. One such drawback is that both the input current and the output current are discontinuous, conducting in one clock phase but not in the other, which is reflected in relatively high output voltage ripple and relatively high induced noise in the system. The amplitude of the inductor current IL is also relatively high, and has relatively high ripple from phase to phase. Transistors T1 and T2 must be constructed to withstand voltages as high as VIN+|VOUT|, necessitating these devices to be relatively large. The transfer function of the inverting buck-boost circuit of FIG. 1a also includes a right-half-plane (RHP) zero, indicating relatively slow transient response.
Another conventional DC-DC voltage converter type is referred to in the art as the Ćuk converter, an example of which is shown in FIG. 1b. This inverting voltage converter includes an inductor L1, a capacitor CF, and another inductor L2, connected in series between the input and output terminals. N-channel MOS transistor T11 has its drain at node N1 between inductor L1 and capacitor CF and its source at ground; similarly, n-channel MOS transistor T12 has its drain at node N2 between capacitor CF and inductor L2 and its source at ground. The gates of transistors T11, T12 receive non-overlapping clock phases ΦA and ΦB, respectively, from a clock generator (not shown in FIG. 1b). In operation, transistor T11 is on and transistor T12 is off during phase ΦA. Inductor current IL1 through inductor L1 conducts through transistor T11 to ground, while inductor current IL2 through inductor L2 charges capacitor CF (via current IFA=IL2). Inductor current IL2 is sourced by load current ILOAD from the output terminal, and output capacitor COUT stabilizes the output voltage VOUT at this terminal. Conversely in phase ΦB, transistor T11 is off and transistor T12 is on, so that current IL1 of inductor L1 charges capacitor CF in the opposite direction (IFB=IL1), and current IL2 through inductor L2 is conducted to ground through transistor T12. This “see-saw” action operates to transfer charge from the input (inductor L1) to the output (inductor L2), in that node N1 is pulled down and node N2 is pulled up during phase ΦA, and node N1 is pulled up and node N2 is pulled down during phase ΦB. The DC transfer function of this Ćuk converter is the same as that of the buck-boost converter, and is similarly dependent on the duty cycle D of phase ΦA:
      V    OUT    =      -                  V        IN            ⁡              (                  D                      1            -            D                          )            
Similarly as the inverting buck-boost topology, the Ćuk converter can produce a negative output voltage VOUT at a magnitude either greater or smaller than that of input voltage VIN. The Ćuk converter operates with both a continuous input current and a continuous output current, greatly reducing ripple in the output voltage VOUT and reducing the switching noise, as compared with the buck-boost converter. However, this topology requires two inductors (or, alternatively, a coupled inductor), which adds cost to the system. And like the inverting buck-boost topology, transistors T11 and T12 must be high voltage devices (rated to VIN+|VOUT|). The transient response of this topology is also relatively slow, because of two RHP zeroes in its transfer function.
As a result, conventional inverting voltage converter topologies do not completely satisfy the need, in some modern system applications, for the generation of a negative output voltage with low ripple and fast transient response. Conventional voltage converters therefore typically include a dedicated post-regulator, such as a negative low-drop-out (LDO) regulator, which reduces the conversion efficiency and also adds to the cost of implementing the voltage conversion function.